Is sGDMA integration correct in this SoC ??

That screenshot is so small I cannot tell which IP in that system is the mSGDMA. In general you hook up a host like the HPS, Nios, etc... to the csr and descriptor slave ports of the dispatcher, the read/write masters to your memory, and if you are performing a streaming transfer the data source/sink to your own streaming IP.

Here is an example showing how the mSGDMA is hooked up to the HPS: https://www.altera.com/support/support-resources/design-examples/soc/fpga-to-hps-bridges-design-example.html

Here is an example showing how the mSGDMA is hooked up to Nios: http://www.alterawiki.com/wiki/modular_sgdma

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That screenshot is so small I cannot tell which IP in that system is the mSGDMA. In general you hook up a host like the HPS, Nios, etc... to the csr and descriptor slave ports of the dispatcher, the read/write masters to your memory, and if you are performing a streaming transfer the data source/sink to your own streaming IP.

Here is an example showing how the mSGDMA is hooked up to the HPS: https://www.altera.com/support/support-resources/design-examples/soc/fpga-to-hps-bridges-design-example.html

Here is an example showing how the mSGDMA is hooked up to Nios: http://www.alterawiki.com/wiki/modular_sgdma

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I will look above on tomorrow morning. Meanwhile I am reuploading the attachment.