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kwangkyu's avatar
kwangkyu
Icon for New Contributor rankNew Contributor
3 years ago

Is it possible to modify Calibration Logic when using External Memory IP on Agilex FPGA?

hello. We are now using Agilex FPGA. We are using External Memory IP, and calibration is performed using Calibration IP. I want to mask some DUTs during calibration through NIOS. Is it possible?
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

As we do not receive any response from you on the previous reply that we have provided, I now transition this thread to community support. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.