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kwangkyu's avatar
kwangkyu
Icon for New Contributor rankNew Contributor
3 years ago

Is it possible to modify Calibration Logic when using External Memory IP on Agilex FPGA?

hello. We are now using Agilex FPGA. We are using External Memory IP, and calibration is performed using Calibration IP. I want to mask some DUTs during calibration through NIOS. Is it possible?
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hello kwangkyu,


Thank you for submitting your question in Intel Community.

I am Adzim and I will assist you on this thread.


The calibration process is in the harden IP that user may not interfere the process.

User may not be able to modify the calibration logic because it's not expose to user logic.


Regards,

Adzim