Is HW breakpoint required for SW breakpoint ?

Hi,

I am trying to add breakpoints to my Nios II Eclipse debug session.

My HW system has not defined any HW breakpoints or Data break points (both explicitly set to 0) in Quartus Platform Design stage. Data triggers also set to 0. Trace type "none".

Jtag debug included, but debugreq and debugack signals NOT included.

In BSP settings:

Allow code at reset is enabled.

alt_load() is enabled.

There's NO rodata or rwdata copy selected for alt_load() during alt_main().

bsp_cflags_debug has option "-g" enabled.

OC ram only has reset and exceptions [via alt_load()]. All of my .text and other code is in Off Chip ddr2 RAM. The code is executed from this Off chip RAM. Reset vector however, points to OC ram which has reset, followed by exceptions.

When I try to add a breakpoint, the debug perspective shows errors.

"cannot access memory at <address> " and "failed to add breakpoint".

The <address> to be accessed is in the Off chip RAM location.
The code flow only stops once at main() and that's it.

From all the documentation, forum search and literature, I could not figure out why this error occurs. The address location in memory is off chip RAM but is R/W (volatile). Hence theoretically, the debugger should be able to insert a software breakpoint instruction. I am NOT debugging boot code and whatever code is present is in R/W memory.

In all the user guides, sw dev handbook, embedded handbook and the IP guide, it is stated that HW breakpoints are needed for boot code debug (non volatile memory, instructions cannot be inserted/overwritten.

If HW breakpoints are needed for SW breakpoints, I have not found it in literature. Of course, there's something else, since the breakpoint is not set.

What am I missing (even theoretically)?

Any other setting(s) to check/set ?

Unfortunately, cannot share any files.

Thanks in advance !

Edit 1 - HW is Cyclone 5

Edit 2 - updated Off Chip RAM as volatile in description