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Honored Contributor
Honored ContributorIRQ handler problem
Hi all, I have build an application on Stratix II, with three CPU's. I have ONE (!) pio line connected to the system of three CPU's. In the SOPC builder I connected the three CPU'...
Altera_ForumHonored Contributor
Honored ContributorYour problem is that the interrupt will interrupt all three CPUs, but obviously they don't all reach the ISR at the same time. One CPU will be first and will have cleared the interrupt before the other ISRs get in, so the software in the ISR will read that there is no active interrupt
The interrupt handler is coded to assume that there must have been an active interrupt, however on some of your CPUs this will not be the case. You could recode the ISR, but you really need to give some more thought to what you're trying to do and design some hardware to cope with one interrupt source going to multiple CPUs
