Thank you.
I received your answer well.
Even after modifying the code according to your answer and debugging it, the same problem occurs.
I think the problem is that I made my CUSTOM IP incorrectly.
If it’s not too much trouble, could you tell me how to make a CUSTOM IP using the UART_TX HDL code I’m providing?
I will write my HDL code for this purpose. I will also attach other HDL codes I wrote to make it into CUSTOM IP below.
// UART_TX
/*
Baud Rate == 1152000, FPGA clock = 50Mhz
Clock per Byte(CPB) = 1152000/20ns = 434
*/
/////////////////////////////
module UART_TX(
input clk,reset_n ,
input [7:0] tx_din ,
input we ,
output done ,
output tx_dout
);
parameter [3:0]
IDLE = 0,
START = 1,
DATA0 = 2,
DATA1 = 3,
DATA2 = 4,
DATA3 = 5,
DATA4 = 6,
DATA5 = 7,
DATA6 = 8,
DATA7 = 9,
STOP0 = 10,
STOP1 = 11;
localparam CPB = 434;
////// wire , reg declaration
reg [3:0] state,next_state ;
reg [9:0] cnt ;
reg dout_reg ;
wire [7:0] din_reg ;
assign din_reg = tx_din ;
//////////////////////////////////////
//state transition logic
always @(cnt,we) begin
next_state = IDLE;
case(state)
IDLE : next_state = (we & cnt == CPB - 1) ? START : IDLE;
START : next_state = (we & cnt == CPB - 1) ? DATA0 : START;
DATA0 : next_state = (we & cnt == CPB - 1) ? DATA1 : DATA0;
DATA1 : next_state = (we & cnt == CPB - 1) ? DATA2 : DATA1;
DATA2 : next_state = (we & cnt == CPB - 1) ? DATA3 : DATA2;
DATA3 : next_state = (we & cnt == CPB - 1) ? DATA4 : DATA3;
DATA4 : next_state = (we & cnt == CPB - 1) ? DATA5 : DATA4;
DATA5 : next_state = (we & cnt == CPB - 1) ? DATA6 : DATA5;
DATA6 : next_state = (we & cnt == CPB - 1) ? DATA7 : DATA6;
DATA7 : next_state = (we & cnt == CPB - 1) ? STOP0 : DATA7;
STOP0 : next_state = (we & cnt == CPB - 1) ? STOP1 : STOP0;
STOP1 : next_state = (we & cnt == CPB - 1) ? IDLE : STOP1;
endcase
end
//state sequantial logic
always @(posedge clk, negedge reset_n) begin
if(!reset_n) state <= IDLE;
else state <= next_state;
end
//i_clk counter
always @(posedge clk, negedge reset_n) begin
if(!reset_n) cnt <= 10'd0;
else begin
if(state != next_state) cnt <= 10'd0;
else cnt <= cnt + 10'd1;
end
end
//output logic
always @(*) begin
dout_reg = 1;
case(state)
IDLE : dout_reg = 1;
START : dout_reg = 0;
DATA0 : dout_reg = din_reg[0];
DATA1 : dout_reg = din_reg[1];
DATA2 : dout_reg = din_reg[2];
DATA3 : dout_reg = din_reg[3];
DATA4 : dout_reg = din_reg[4];
DATA5 : dout_reg = din_reg[5];
DATA6 : dout_reg = din_reg[6];
DATA7 : dout_reg = din_reg[7];
STOP0 : dout_reg = 1;
STOP1 : dout_reg = 1;
endcase
end
assign tx_dout = dout_reg;
assign done = (state == STOP1);
endmodule
// HDL CODE FOR USING CUSTOM IP
module TX_IP(
input clk,reset_n,
output done,q_ex
);
Qsys_default u0 (
.clk_clk (clk), // clk.clk
.reset_reset_n (reset_n), // reset.reset_n
.tx_dout_qsys_0_conduit_end_export (q_ex), // tx_dout_qsys_0_conduit_end.export
.done_0_conduit_end_1_export (done) // done_0_conduit_end_1.export
);
endmodule
////////////////////////////////////////////////////////////
Thank you again for your dedication.
Thanks to this community, I was able to grow quickly
/////
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