Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

IORD takes 20 cycles??

Hello, We are having IORD performance problem with Nios II Cyclone III 3C25F324 fpga. In our design we aru using CPU at 100MHz clock, and we have some custom fpga blocks. We need to read reg...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Because of another problem we couldn't work on these issues. In a few days we will return this issues again, I will share the results of your improvment advices.

Currently we are using a single clock very simple custom instruction, but we will implement more complex custom instructions. I guess we will see if rA/rB stalls :).. I hope we can come with a solution..

Thanks again..