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Altera_Forum
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15 years ago

IORD takes 20 cycles??

Hello, We are having IORD performance problem with Nios II Cyclone III 3C25F324 fpga. In our design we aru using CPU at 100MHz clock, and we have some custom fpga blocks. We need to read reg...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

First of all, thank you for quick reply.

I am a software guy who is new at NIOS CPU and who is completely novice about the fpga stuff.

Bu as far as I know,

*Yes, the fpga blocks are working at 50Mhz (slower than CPU).

* And I will check wit the fpga designer if the avalon slave is 32bits and if we are using M9K blocks or not.

As you mentioned, we used a few custom instructions and they are pretty fast.

I wonder if we can read the registers of custom fpga blocks from another custom instruction? Would such a design cause conflict of master-slave relations?