IORD IOWR macros vs. memory access to peripherals

hey guys im new to sopc,nios design..

my intention is to instantiate nios2 n sram .do read write operations via c program.

i configured FPGA with nios2 processor and SRAM from university programm(DE1 BOARD,CYCLONE). IF WE HAVE MACROS TO ACCESS MEMORY THEN what about the pins of sram. how do i write into those pins in C language. we suppose to write in memory mapped memory adresses of pins assigned by SOPC . but it wont giv address map for those controll pins of sram. it only states initial address of sram.

pls help..

this is instantiated VHDL code.

component rams is

port (

-- 1) global signals:

signal clk_0 : IN STD_LOGIC;

signal reset_n : IN STD_LOGIC;

-- the_income

signal in_port_to_the_income : IN STD_LOGIC_VECTOR (7 DOWNTO 0);

-- the_outgo

signal out_port_from_the_outgo : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);

-- the_sram_0

signal SRAM_ADDR_from_the_sram_0 : OUT STD_LOGIC_VECTOR (17 DOWNTO 0);

signal SRAM_CE_N_from_the_sram_0 : OUT STD_LOGIC;

signal SRAM_DQ_to_and_from_the_sram_0 : INOUT STD_LOGIC_VECTOR (15 DOWNTO 0);

signal SRAM_LB_N_from_the_sram_0 : OUT STD_LOGIC;

signal SRAM_OE_N_from_the_sram_0 : OUT STD_LOGIC;

signal SRAM_UB_N_from_the_sram_0 : OUT STD_LOGIC;

signal SRAM_WE_N_from_the_sram_0 : OUT STD_LOGIC

);

end component rams;

it gives mem mapped adress of income n outgo(these r pio_0 n pio_1).

but not for other signals out there.