IORD IOWR macros vs. memory access to peripherals

Actually what might happen is that initially the code will write out the expected values, however at a later time any data lurking in the cache might be written out - overwriting the data written with IOWR_32DIRECT().

An example using malloc() is a bad one - since you need to ensure the data you are accessing uncached (or with specific cache flushes/invalidates) is cache line aligned, otherwise unexpected behaviour will happen at the ends of the area. This is especially true if you have other Avalon MM masters writing into the memory area. However, for areas like ethernet frame buffers it may be necessary to use cached accesses (to get adequate performance) even though the ethernet hardware writes into the data area.

On x86 (and some others) processors this isn't a problem because the cache snoops the other memory accesses.