Interrupts

Hi Banx,

> I'd like to be able to allow other interrupts of the same priority to occur during the ISR.

> Is there a software method to do this?

Interrupt "priority" is purely a software concept -- the controller supports up to

32 bits -- the order you process them is controlled only by software.

That said, you can disable the particular interrupt that (as you say) 'sticks' by

clearing the bit in the ienable control register. After you do this, you can re-enable

interrupts via PIE. To prevent nesting of the one that 'sticks' your interrupt dispatch

code can AND the ienable and status register contents -- and use the result to

determine if you should call the handler. The u-boot code uses this technique. e.g.:<div class='quotetop'>QUOTE </div>

--- Quote Start ---

void external_interrupt (struct pt_regs *regs)

{

unsigned irqs;

struct irq_action *act;

/* evaluate only irqs that are both enabled and pending */

irqs = rdctl (ctl_ienable) & rdctl (ctl_ipending);

act = vecs;

/* Assume (as does the Nios2 HAL) that bit 0 is highest

* priority. NOTE: There is ALWAYS a handler assigned

* (the default if no other).

*/

while (irqs) {

if (irqs & 1) {

act->handler (act->arg);

act->count++;

}

irqs >>=1;

act++;

}

}[/b]

--- Quote End ---

Regards,

--Scott