Honored Contributor
Honored Contributor--- quote start ---
<!--quotebegin-hippo@Oct 25 2006, 03:13 PM in general, you should use level trigger interrupt, which should be more reliable for linux.
since the source of interrupts are inside the fpga, there is no need to use pio for edge trigger.
you should generate level trigger interrupt, and drive it directly to cpu.
then clear the interrupt request in your service routine.
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--- Quote End --- Thank you for your reply. We will start using level trigged interrupts, but this does not affect the DMA controller interrupts. I have created a module to test DMA transfer only, and I still get extra interrupts with status 0x00. See source code below. The invalid interrupt is trigged in addition to the correct interrupt. How is this possible? Can this be a hardware related error? [/b] --- Quote End --- Here is some more information regarding the problem. I have taken a screen shot from our oscilloscope: image from oscilloscope (http://www.gustavsen.cc/images/interrupts.png) Channel 1 is a pulse trigged from my interrupt handler. The short pulses are OK, but the long pulse indicates that the interrupt handler is called even if the interrupt signal is low, which should not be possible. Channel 2 is the interrupt signal. The signal is set high by the FPGA when data is written to a FIFO and cleared by my interrupt handler. The long pulse here indicates that the interrupt is handled much later than usual. The previous and next interrupts are OK. This situation happens at with even intervals. The interval depends on the interrupt rate. Sometimes it is every 4 seconds, and sometimes it is every 17s. My question is why the interrupt handler is called later sometimes, and is it possible for the kernel to trig interrupt handlers without an external interrupt? As I mentioned in my earlier post, we have this problem with DMA too, but AFAIK we cannot probe DMA interrupt with the scope since it is internal in NIOS. Do you have any tips for further troubleshooting? Regards Hein Gustavsen
