interfacing to custom logic with an interrupt

I have made an interface to custom logic using an avalon slave port with the following signals,

clk, irq, readdata, address, read, chipselect

the idea is that custom logic can set the irq line high, wait for the nios-ii to read the data, then set it low again.

However in practice, the sotfware creates the interrupt OK, goes into the ISR, but never calls the DSR, and if I try to read from the port in the ISR, it seems to read the data, but never sends a read or chipselect signal,

below is some code excerpts

creating the interrupt in cyg_user_start...

   
  cyg_handle_t intrpt_handle; 
  cyg_interrupt intr_mem;
  
  diag_printf("Initialising the interrupt\n");
   
  cyg_interrupt_create( INTERRUPT_INTERFACE_0_IRQ, 
        0, 
        0, 
        &isr_interrupt_interface, 
        &dsr_interrupt_interface, 
        &intrpt_handle, 
        &intr_mem);
 cyg_interrupt_attach( intrpt_handle);
 cyg_interrupt_unmask(INTERRUPT_INTERFACE_0_IRQ);

the isr and dsr...

cyg_uint32 isr_interrupt_interface(cyg_vector_t vector, cyg_addrword_t data)
{
    volatile unsigned short *isr_reg_addr = (unsigned short *)INTERRUPT_INTERFACE_0_BASE;
    
   // Block this interrupt from occurring until
    // the DSR completes.
    cyg_interrupt_mask( vector );
    // Tell the processor that we have received
    // the interrupt.
    cyg_interrupt_acknowledge( vector );
    isr_data = *isr_reg_addr;
    bldy_isr++;
   return  CYG_ISR_CALL_DSR;
}
void dsr_interrupt_interface(cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t z_isr_data)
{
    volatile unsigned short *isr_reg_addr = (unsigned short *)INTERRUPT_INTERFACE_0_BASE;
    //bldy_isr++;
    isr_data++;// = *isr_reg_addr;
    cyg_interrupt_unmask( vector );
}

bldy_isr and isr_data are two global variables that I can use to check what is happening

Can someone give me a few clues as to what to do find out why the DSR is not called, and also I cannot find any documentation as to how long the irq must be asserted for. The avalon interface specification says...

<div class='quotetop'>QUOTE </div>

--- Quote Start ---

9.1.1. Slave Interrupt Signal: irq

... The peripheral logic must assert irq continuously until a master port explicitly resets the interrupt request.[/b]

--- Quote End ---

How does a master port reset the irq?