interfacing to custom logic with an interrupt

Hi manns,

> I cannot find any documentation as to how long the irq must be asserted for.

See the "Nios II Processor Reference Handbook", the sub-section entitled, "Integral Interrupt Controller".

IRQ signals are level-sensitive. So, they must be asserted until explicitly negated (in most cases

by the CPU data master as a result of a software action). The bottom line is your logic must

maintain the level at least long enough for the interrupt to be recognized (CPU transfers

execution to the exception address) and the exception handler identifies the specific IRQ that

caused the exception.

> The avalon interface specification says...

>

> Slave Interrupt Signal: irq

> ... The peripheral logic must assert irq continuously until a master port explicitly resets the interrupt

> request.

>

> How does a master port reset the irq?

In most cases your software will read a register, clear/set a bit, whatever. This is up to you ...

some mechanism your custom logic provides.

Regards,

--Scott