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Altera_Forum
Honored Contributor
14 years agoIt is easier than you think
Instantiate this way: AES_128_EncryptionCore u0(clk,key,PlainText,Load,reset,CipherText,Done); You only need to add this glue logic: wire key[127:0] = { user_dataout_4, user_dataout_3, user_dataout_2, user_dataout_1 }; wire PlainText = user_dataout_0[0]; wire Load = user_dataout_0[1]; wire CipherText wire Done; assign user_datain_0[0] = CipherText; assign user_datain_0[1] = Done; Here I assumed these register functions: - the AES key is stored into user_dataout_1 to 4 - user_dataout_0 is a 'control register', where bit 0 is used as data input and bit 1 as load command - user_datain_0 is a 'status register', where bit 0 is your encrypted data output and bit 1 is the completion signal. Please note that this is a minimal addresses implementation; these 4 bits can be as well mapped singularly on 4 separated registers. If you want a smarter code, replace all those user_data_ with the actual register functions, eg control_reg,status_reg,key0,key1,...