Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Interconnections and interrupts between nios processors

Hi, Now I am working on multi-core systms. Based on altera platform, more than two processors are using in a system and shard memory (message buffe) with Avalon-MM Pipeline Bridge is selected ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

To lethenstrom,

Thank you very much!

A custom interrupt controller would be a nice option for me. If a multi-core system includes more than two processors, how it would work by using dual port memory? Or more dual port memory blocks are involved(this is the reason I want to use pipeline bridge, but I don't know how to transfer interrupt signals between processors in Qsys)?