Forum Discussion
Altera_Forum
Honored Contributor
14 years agoTo lethenstrom,
Thank you very much! A custom interrupt controller would be a nice option for me. If a multi-core system includes more than two processors, how it would work by using dual port memory? Or more dual port memory blocks are involved(this is the reason I want to use pipeline bridge, but I don't know how to transfer interrupt signals between processors in Qsys)?