Honored Contributor
Honored Contributorhttp://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/biggrin.gif I've now fixed the problem - but the resolution may be useful to others.
When you do any erase/program/lock/unlock operation on an Intel flash chip, the HAL checks the status register to verify correct operation, which works fine. But one poorly documented aspect in the Intel datasheet is that any error bits in the status register remain set until you do a "Clear Status Register" (0x50) command. The HAL never does this, which may be an issue if an erase or program ever fails. Probably the CPLD boot sequence on our board performs spurious writes to the flash, setting the "Command Sequence error" bits. Because they're never cleared, all my subsequent programming attempts were failing. I've added a "Clear Status Register" command at the beginning of the Erase Block code, and everything now seems to be working fine. Onwards and upwards.... -Roddy
