Forum Discussion
Altera_Forum
Honored Contributor
15 years agoI'm not used to System Verilog and can't decide, if the said behaviour is an issue of the Quartus implementation or expectable by design. But System Verilog has also localparam for constants, that is accepted by Quartus in this case. The specification clarifies, that const is intended to be changed at simulation runstime.
P.S.: I noticed, that you aparently referred to C rather than System Verilog, although the behaviour is basically similar. In C, a const object is processed like a RAM variable, although it can't be written at runtime. So the compiler doesn't treat it as a constant value. I think, it's common to all C compilers.