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Altera_Forum
Honored Contributor
21 years agoActually he need-not re-generate in SOPC Builder. The common_ram HDL file is already set to initialize using the .hex file the IDE may (or may not) produce. You should verify that such a .hex file is there, and has some bytes in it that look like initialization data. Then, re-compile in Quartus. This will initialize the on-chip RAM with the contents of the .hex file and include that with the FPGA's programming file.