Honored Contributor
Honored Contributor
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the memory in terms of timing works fine because i tested it using labview making calls to fs2's mdi to perform adderss/data bus tests, etc... --- Quote End --- But, how do you get the sdram pins work fine? The IDE display download info, then verify failed. Do you know that what will be done in verify process and what is the sdram pins state? Thank you, LiangYi <div align='right'><{post_snapback}> (index.php?act=findpost&pid=12281)</div> [/b] --- Quote End --- If I understand what you are asking -- From talking with other users, if you have "boarderline" timing issues with memory doing peeks and pokes to a few memory locations will not always show a problem. Peeks and pokes only help show "major" timming issues or incorrectly connected memories. If you hit the memory with a large block of data transfers the "boarderline" memory timing issues will start to up. For example 1) A DMA transfer to memory and back shows different results 2) If you load your program into SDRAM memory that has borderline timing issues, the processor is always accessing its next instruction so the memory problems will show up quickly by your program locking up. 3) If you use the IDE download a new program onto your board (writes are ok) and it fails verify (read fails) then one cause could be memory timing or I incorrectly connected the memory.
