Forum Discussion
Honored ContributorINCLUDE SOFTWARE INTO EPCS (.jic)
Hello,
i tried many different method on how to include my software for nios2 processor (.elf file) into the jic file together with the .sof fpga file. I have an fpga with a nios2 processor. I have only the processor and an on-chip ram. My simple software just turn on and off 4 leds. if i load the .sof file first with quartus programmer and then run the Eclipse IDE to debug the software all works, but when i create a single .jic file to program the epcs nothing works. I would like to know the procedure to include both fpga .sof file generated by quartus compilation and .elf file that include my software into a single .jic file. Thanks for your help12 Replies
Altera_Forumright here ;)
http://www.alteraforum.com/forum/showthread.php?t=31375- Altera_Forum
thanks for the link but i already tried that solution and doesn't work.
Maybe i had to insert more information about the reset vector during the conversion process? Are there some options that i had to set in Eclipse IDE or Qsys project? - Altera_Forum
Check the reset vector of your processor in SOPC Builder. It has to be at "epcs_flash_controller".
- Altera_Forum
i think that i miss something.
In my qsys project i don't have a flash controller, just a nios processor and an on-chip memory (RAM). - Altera_Forum
OK.
Your processor has a reset vector which tells it the adress where it has to begin to load the code. When you use eclipse to load the code, the reset vector set at Onchip_ram is good because eclipse writes directly the RAM by JTAG. But when you want to load the software from a flash memory, you have to tell the processor to take the code from this flash by his own. And that is what the "epcs_flash_controller" do. This IP has a small ROM which contains some code. This code only read a flash memory and tells the processor to start from here. So add this IP in your Qsys, set the reset_vetor in your processor IP and it should starts. - Altera_Forum
You can also use your code to initialise the on-chip memory as part of the normal FPGA initialisation (via a .HEX file).
In this case the reset vector points directly into the on-chip memory. This saves the fpga resources used for the EPCS bootloader, but means that you can't restart the code without a full fpga reset. - Altera_Forum
how can i add my .hex as part of the FPGa initialization?
- Altera_Forum
First you need to create the hex file from the elf file. Start the NIOS command shell and use the elf2hex command to do that. Make sure you convert the entire on-chip memory to a hex file. Once you have the hex file preload the on-chip memory in Qsys with that hex file you just created. Then recompile the project. jic in the resulting configuration file into your configuration flash. when you power up your FPGA now it will be configured from flash and the onchip memory will be preloaded with your hex file.
Hope that helps /Boris - Altera_Forum
Forgot one thing. Make sure your reset vector and exception vector is in the onchip memory as well.
/Boris - Altera_Forum
hello,
i have still some problem. my on-chip memory is set to: Type: RAm writable Blocktype:auto Data width: 32 memory size:4096 bytes i check: Initialize memory content Enable non-default initialization file User created initialization file: "my_file.hex" this on-chip memory has BASE:0x00100000 ; END 0x00100fff the nios2 cpu has reset vector set to:0x00100000 in the nios shell i wrote: elf2hex --input=my_file.elf --width=32 --base=0x00100000 --end=0x00100fff --output=my_file.hex then i re-generate the qsys system and recompile all the fpga sustem in QuartusII, downloaded the .sof through jtag but nothing works Where is the error? Thanks
