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Oliver_I_Sedlacek's avatar
Oliver_I_Sedlacek
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3 years ago
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Improving NIOS2 performance, problems with memory map

My starting point was a project for the Trenz CYC1000 which couples a Cyclone 10 LP with a 64M bit SDRAM memory chip. I'm successfully developing and running a NIOS2 application but the performance i...
  • Oliver_I_Sedlacek's avatar
    Oliver_I_Sedlacek
    3 years ago

    Thanks for that. I've looked at the description of mgptop and I'm not really any the wiser. In the mean time I've got it to link by putting onchip memory just below the SDRAM so there aren't big gaps in memory space. There look to be a lot of settings that should improve performance (e.g. separate interrupt stack) but I'm guessing a lot of them may also just break the project. I'm reluctant to change anything I don't really understand.

KellyJialin_Goh's avatar
KellyJialin_Goh
Icon for Frequent Contributor rankFrequent Contributor
3 years ago

Hi,

Thank you for your response. I agree with your statement as it changes the algorithm behind that you do not understand.

Anyway, is linking onchip memory just below the SDRAM the workaround to bypass the issue?


Hope to hear on your feedback.


Thank you.

Regards,

Kelly


Oliver_I_Sedlacek's avatar
Oliver_I_Sedlacek
Icon for Contributor rankContributor
3 years ago

Yes, I could put .bss, .stack and .rwdata in onchip RAM and throughput has improved significantly to where it needs to be. I think what I will try is switching to the 'full fat' NIOS2 as that includes caches, which is what I really need. It's a shame there's not a bit more granularity in some of these options.