Forum Discussion
Altera_Forum
Honored Contributor
15 years agoHi,
I never used the pio edge capture feature, but from pio datasheet I believe usage is correct. As I suggested before, maybe the problem is due to bounces on rdclk or slow edges which cause multiple triggering of edge capture function. I'd try to filter rdclk; but first of all I think rdclk needs to be synchronized to system clock (yes, I mean Nios/sopc clock): infact, I think the pio module uses this clock to sample rdclk and detect edges rather than using the pio input to clock the edge register high. Another test which may help to identify the problem is excluding edge capture and make a manual double sampling. This way:
while( 1 ) {
/* wait until rdclk goes low */
do {
clk_stat=IORD_ALTERA_AVALON_PIO_DATA(CH1_RDCLK _BASE);
} while ( clk_stat & 1);
/* wait until rdclk goes high */
do {
clk_stat=IORD_ALTERA_AVALON_PIO_DATA(CH1_RDCLK _BASE);
} while ( (clk_stat & 1)==0);
if (IORD_ALTERA_AVALON_PIO_DATA(CH1_RDEN_BASE) & 1) {
ch1_data = IORD_ALTERA_AVALON_PIO_DATA(CH1_PIO_BASE);
printf("%02x, ", ch1_data);
}
}
Note that I used a bit compare (&) instead of full compare (==). I don't know the status of other bits in the register. They could be indeterminate: maybe this is your mistake. Regards Cris