Forum Discussion
Altera_Forum
Honored Contributor
14 years agoHi,
If you're using Qsys, you can try the "Generic tristate controller", and adjust it with the parameters of your memory looking on its datasheet not forgetting to define it as a "memory device". For earlier versions and without a generic controller, you should write your own wrapping into SOPC. That means that you write a verilog or VHDL file that maps the memory pins into the avalon bus, it's something like thismodule SRAM_16Bit_512K(// Host Data
oDATA,iDATA,iADDR,
iWE_N,iOE_N,
iCE_N,iCLK,
iBE_N,
// SRAM
SRAM_DQ,
SRAM_ADDR,
SRAM_UB_N,
SRAM_LB_N,
SRAM_WE_N,
SRAM_CE_N,
SRAM_OE_N
);
// Host Side
input iDATA;
output oDATA;
input iADDR;
input iWE_N,iOE_N;
input iCE_N,iCLK;
input iBE_N;
// SRAM Side
inout SRAM_DQ;
output SRAM_ADDR;
output SRAM_UB_N,
SRAM_LB_N,
SRAM_WE_N,
SRAM_CE_N,
SRAM_OE_N;
assign SRAM_DQ = SRAM_WE_N ? 16'hzzzz : iDATA;
assign oDATA = SRAM_DQ;
assign SRAM_ADDR = iADDR;
assign SRAM_WE_N = iWE_N;
assign SRAM_OE_N = iOE_N;
assign SRAM_CE_N = iCE_N;
assign SRAM_UB_N = iBE_N;
assign SRAM_LB_N = iBE_N;
endmodule Then you have to create the SOPC component that gives the _hw.tcl with "file/new component..."