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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
21 years ago

IDE Compiler features?

Hi!

I have a question about IDE compiler features.

I've made a board with CFI flash and Ethernet controller

on the same tri-state bridge. CFI flash (data 8 bits) has dynamic

alignment (A[0] = A[0]) and Ethernet controller (data 8 bits) has

native alignment (A[0] = A[2]). But when I was tracing my board I've

made error and put A[0] of Ethernet controller to A[0] of tri-state

bridge.

I've tried to describe ethernter controller as memory device (dynamic

alignment) and created next structure for it in C:

....................# pragma pack(1)

typedef struct _cs8900

{

unsigned char DATA0L;

unsigned char DATA0H;

unsigned char DATA1L;

unsigned char DATA1H;

unsigned char TxCMDL;

unsigned char TxCMDH;

unsigned char TxLENGTHL;

unsigned char TxLENGTHH;

unsigned char ISQL;

unsigned char ISQH;

unsigned char PACKETPAGE_POINTERL;

unsigned char PACKETPAGE_POINTERH;

unsigned char PACKETPAGE_DATA0L;

unsigned char PACKETPAGE_DATA0H;

unsigned char PACKETPAGE_DATA1L;

unsigned char PACKETPAGE_DATA1H;

} cs8900;# pragma pack()

volatile cs8900 *p =(cs8900*) CS8900_BASE;

....................

but when I'm reading p->DATA0L or p->DATA0H there is always zero.

When I'm writing there is OK. And in generaly it works.

I think that compiler generetes code for my controller something wrong

and because of that I can't read p->DATA0L and p->DATA0H correctly.

Maybe someone has any idea?

Thx.

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    HI Camelot,

    I am doing the same projet , Do you have resolve the problem? I thank the there are errors in the avalon bus,Could you contact with me ? my mail:nwpu_zhfeng@126.com