I2C bus in vhdl file

In VHDL, when you declare the entity, you define a port list. In this port list is where you specify what signals are input/output/bidir to the 'function'. You can look at the simple example at the end of my post.

The following is going to to be quartus specific. To get your signals to actual FPGA pins do the following: Once you complete your entity, you can create a schematic symbol for your entity by loading your VHDL in Quartus, and then going to File -> Create/Update -> Create Symbol Files for Current File. Once you do so, you'll be able to place a symbol of your VHDL entity on a schematic (double click a blank schematic and navigate to your project). and connect it's traces to Input or Output symbols. From there, you can goto Assignments -> Pin Planner and connect at will.

Let me know if you need any details on any specific step.

VHDL Example (P.S. This code does not perform any (useful?) function):

--------------------------------------------------------------------------------
-- Kevin Wolfe
-- This is a comment
--------------------------------------------------------------------------------
-- Rev.  0 - 08/14/06 - KDW - Inception
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.all;
USE ieee.STD_LOGIC_unsigned.all;
---------------------------------------------------
ENTITY RAM_MANAGER IS
PORT(
    clk      :    IN  STD_LOGIC;
    mcu_data    :    IN  STD_LOGIC_VECTOR(7  DOWNTO 0);    
    addr_dec    :  OUT  STD_LOGIC);
    
END RAM_MANAGER;
----------------------------------------------------
ARCHITECTURE behv of RAM_MANAGER IS
    CONSTANT SOME_CONSTANT_NAME      :    integer := 2;
    SIGNAL    some_singal_i  : STD_LOGIC_VECOTR(8 DOWNTO 0)    := (OTHERS => '0');
    
    SIGNAL    count_i      : INTEGER range 0 to READ_PERIOD    := 26;
BEGIN
    -- Process to respond to read Requests
    PROCESS (clk)
    BEGIN
  CASE (conv_integer(mcu_data)) IS
      WHEN 0 =>
    some_singal_i <= &#39;1&#39;;
      WHEN 1 =>
    some_singal_i <= &#39;0&#39;;
      WHEN 2 =>
    count_i    <= count_i + 1;
      WHEN OTHERS      =>
  END CASE;
    END PROCESS;
    
    addr_dec <= some_singal_;
END behv;