I need some help of creating shared ddr sdram memory

That is correct, the reason for this is that tightly coupled memory cannot stall the processor pipeline, so the slave port cannot be shared as arbitration could cause waitstates.

From my own testing I find that worst case random access patterns to SDRAM will drop the performance down to 33% efficiency. Best case is around 97% but you would need something like a DMA to hit that. A cache I suspect should achieve around 90% as most SDRAM controllers have built in management for the rows/columns/banks (or whatever SDRAM people call those terms). Due to the mapping of the cache lines in the address space the first access will typically have some overhead but the next seven accesses (assuming 32B/L) should enter the controller efficiently assuming the arbitration share is set to 8 or greater so that other masters don't get in and start thrashing the memory.