I need some help of creating shared ddr sdram memory

I did some measurements for random uncached SDRAM accesses.

IIRC the first 2 writes happen without significant delay. I suspect that the first one is actioned asynchronously, and the second is put into an SDRAM 'line' buffer (32 bytes ?) in case the next transfer is to the same SDRAM line.

It is also likely that SDRAM reads always read a memory line, and Avalon reads that match the buffered data (eg sequential access) are completed without doing an actual memory transfer.

However cache transfers should be faster since (I think) they get pipelined.

Unfortunately the nios cpu is missing the instruction to create a valid cache line without doing the memory read (useful when you know you are going to modify the entire line). I think there are some other missing cache functions that rather hurt attempts to run unix os.