I need some help of creating shared ddr sdram memory

That's correct, the mailbox component is similar to a FIFO only parts of it are implemented in software which is why it's slow when sending small messages back and forth. The good part is that it's scalable to any memory in your system. Using the FIFO approach I either drain the FIFOs until they are empty or map the FIFO 'used' signal so that I know ahead of time how much data I can safely read out of it if I don't want to end up blocking the processor when the FIFO is empty. Sometimes I make this interrupt based as well.

The on-chip memory if it's connected directly to the (regular) Nios II data master when the data cache is enabled will be cacheable. Think of the tightly coupled master and caches being in parallel inside the processor, the decode to determine if the access is tightly coupled, cacheable, or uncacheable happens concurrently. Just remember that the Nios II JTAG debugger can't download instructions into tightly coupled memory unless there is a data master connection to the tightly coupled memory (regular or tightly coupled).

If you decide to make the on-chip RAM cacheable you can carve out some of that memory and remap it to be uncacheable so that you don't need to use IOWR/IORD to access the shared data. If you do this use the HAL calls that remap the pointer and don't explicitly flip the MSB of the pointer manually since there is some cache considerations that the HAL takes care of.