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APaul's avatar
APaul
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7 years ago

I can not get Passive Serial Configuration to work on a Cyclone 10 GX FPGA.

In my design, an mcu SPI port is used to send the configuration file. The software that does this was tested and verified using a Cyclone IV FPGA and worked fine. We are now re-using this same so...
a_x_h_75's avatar
a_x_h_75
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7 years ago

How clean is DCLK at the FPGA pin (or as close as you can get to the pin)? Slowing DCLK is sensible. However, if you have any inflections at the pin then the FPGA may interpret these as additional clock edges and clock in extra, unwanted bits. nSTATUS going low during configuration is entirely consistent with this behaviour. Slowing DCLK won't overcome this issue. Do you have a source termination resistor by your DCLK source driver?

Sorry to ask, but have you compiled/created rbf for the correct part?

Bit order often catches people out, although I appreciate you're reusing previously proven code.

Cheers,

Alex