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APaul's avatar
APaul
Icon for New Contributor rankNew Contributor
7 years ago

I can not get Passive Serial Configuration to work on a Cyclone 10 GX FPGA.

In my design, an mcu SPI port is used to send the configuration file. The software that does this was tested and verified using a Cyclone IV FPGA and worked fine. We are now re-using this same software to load an Cyclone 10 GX, but all attempts result in fail. We have slowed down the DCLK to 1MHz just to eliminate speed as an issue. During each attempted load, nSTATUS is seen being pulled low by the FPGA to indicate an issue. INIT DONE never goes low like it should after the first frame. This makes me question whether the RBF file was created correctly. Any suggestions on how to proceed troubleshooting this ? Exact part is 10CX220YF672E5G

2 Replies

  • YuanLi_S_Intel's avatar
    YuanLi_S_Intel
    Icon for Regular Contributor rankRegular Contributor
    7 years ago

    Hi Apaul,

    Have you checked whether if the timing is clean during the compilation of the quartus project?

    Regards,

    YL

  • a_x_h_75's avatar
    a_x_h_75
    Icon for Contributor rankContributor
    7 years ago

    How clean is DCLK at the FPGA pin (or as close as you can get to the pin)? Slowing DCLK is sensible. However, if you have any inflections at the pin then the FPGA may interpret these as additional clock edges and clock in extra, unwanted bits. nSTATUS going low during configuration is entirely consistent with this behaviour. Slowing DCLK won't overcome this issue. Do you have a source termination resistor by your DCLK source driver?

    Sorry to ask, but have you compiled/created rbf for the correct part?

    Bit order often catches people out, although I appreciate you're reusing previously proven code.

    Cheers,

    Alex