Altera_ForumHonored Contributor10 years agoHPS DDR memory access for Preloader and UBoot I have a Cyclone V board with 1Gbyte DDR3L memory connected up to the HPS. I am loading U-Boot through the Preloader using UART0 and YModem transfers from my PC. This all works, and I can see U-Boo...Show Moremultiple-attachments.zip40 KB
Altera_ForumHonored Contributor10 years agoyou are using cyclone based ghrd for cyclone board and denano ghrd for denano board?
Recent DiscussionsMultiple NIOS V ImplementationSolvedImplementing many Nios® V cores on Agilex™ 7not able to use multiple niosV cores at the same timeSysID TimestampLPDDR4 not available in NIOSV/g linker script - Agilex-5, Quartus 26.1 Pro