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Altera_Forum's avatar
Altera_Forum
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21 years ago

How to validate ram and stack size

I have been fighting to get a NIOS II system going. One of the problems I have faced I suspect to be stack overflows. This makes me ask if you have some good ideas on how to

a) detect that stack overflow has indeed occoured.

c) predict or measure how large stack will be needed in a running system.

The same could be asked about the heap requirements.

I have thought about the following for the stack problem but possibly also useful to check heap size:

fill the ram with a known pattern, and after the system has run or is running, read the ram and find how far down (for a stack growing towards 0) the ram has been changed. A function which goes through the ram looking for the fill pattern could map out any unused ram, giving an indication of heap usage as well. Filling of the ram could be tricky as one would not want to overwrite anything of value.

Are there a trick with the linker which could be used?

hardware peak stack value register

Given the unique feature of a "semi-soft" processor core it would be useful to build a hardware stack pointer monitor into the core. A kind of peak-finding register, which always tracks the minimal value of the stack (again for a downgrowing stack). Initialize it at startup to point to the top, and read it later to see how far down it went! Easy in principle, but requires access to nios code. I dont think it would fit as a custom instruction thing.

When having an operating system, one would have to deal with the task switching, which relocates the stack to the memory block for the running task. The peak stack value register would in that case have to be managed by the OS as one would have a peak stack value per task.

I have not tried any of these ideas. I am sure there are other solutions! Aren't there?

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    21 years ago

    Can be try "Data Triggers"? ( n2cpu_nii5v1.pdf file, page 4-5).

    " This refers to the ability to trigger on arbitrary conditions on the instruction and data bus

    during execution. You can set a trigger to activate based on address value, data value,

    or read or write cycle.

    Triggers are more versatile than simple breakpoints. You can use a trigger like a

    breakpoint to halt the processor on specific events or conditions. Furthermore, you can

    use a trigger to activate other events, such as starting execution trace, or sending a

    trigger signal to an external logic analyzer. Two data triggers can be combined to form

    a trigger that activates on a range of data or addresses. "

    It may catch some data bus conditions as "write" for example.

    For example Stack size = 1024, SP base = 0 and data trigger set to 512. When core try write to address 512 the data trigger set event.