Honored Contributor
Honored Contributor<div class='quotetop'>QUOTE </div>
--- Quote Start --- Let's say we removed the two lines syaing Input1 <= Input1. The compiler seeing that will not know what to do when the address seen is not "000". What it will do is generate a latch to keep the data in Input1 the same as it was. This is done without you knowing about it and is not desirable (latches in FPGAs are bad things). So, these lines actually make sure that the compiler knows what to do with each of the registers in each of the cases it may encounter. This prevents these transparent latches from being instantiated.[/b] --- Quote End --- Ok now I see. <div class='quotetop'>QUOTE </div> --- Quote Start --- Regarding the problem you are seeing in software: It's possible that you defined the polarity of the Nios control signals (or one of them) wrong when you added the peripheral to the SOPC builder ?[/b] --- Quote End --- This is possible, I will check the settings tommorow. Another question: is it possible that my peripheral needs some time to provide the result, so I have to wait a liitle bit before reading from it? How can I determine that my peripheral is ready for reading from it?
