Honored Contributor
Honored ContributorHello Qwerty
Here are the answers to your questions: <div class='quotetop'>QUOTE </div> --- Quote Start --- I mapped the "output" signal to type export because it's a not-avalon signal, right?[/b] --- Quote End --- This is right. <div class='quotetop'>QUOTE </div> --- Quote Start --- Why are the expressions like input1 <= input1 needed? For me they don't make any sense.[/b] --- Quote End --- Let's say we removed the two lines syaing Input1 <= Input1. The compiler seeing that will not know what to do when the address seen is not "000". What it will do is generate a latch to keep the data in Input1 the same as it was. This is done without you knowing about it and is not desirable (latches in FPGAs are bad things). So, these lines actually make sure that the compiler knows what to do with each of the registers in each of the cases it may encounter. This prevents these transparent latches from being instantiated. Regarding the problem you are seeing in software: It's possible that you defined the polarity of the Nios control signals (or one of them) wrong when you added the peripheral to the SOPC builder ? <div class='quotetop'>QUOTE </div> --- Quote Start --- And the last question: in this example we in principle can access eigth 32-bit input ports and eigth 32-bit output ports (because address is a 3-bit value), right? What if I want to have lets say two 3-bit input ports, one 1-bit input port, one 32-bit input port and one 1-bit output port? How do I have do declare them in the vhdl-code and access them from them SW?[/b] --- Quote End --- I defined the peripheral to use a 3 bit address bus, meaning the address space is 8 addresses. Each address can have its own data width (from 1 to 32 bits). If ou add one more bit to the address space you can have 16 different addresses. These addresses are registers addresses. Each register can be either Read only, write only or read-write. I hope this ansewrs your question. Nir
