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Altera_Forum
Honored Contributor
21 years agoHi Owerty
Look at this code:library IEEE;
use IEEE.std_logic_1164.all;
ENTITY example IS PORT (
clk : IN STD_LOGIC;
nreset : IN STD_LOGIC;
-- Nios interface
Nios_Cs : IN STD_LOGIC;
Nios_Rd : IN STD_LOGIC;
Nios_Wr : IN STD_LOGIC;
Nios_Addr : IN STD_LOGIC_VECTOR(2 DOWNTO 0); -- just an example
Nios_Din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
Nios_Dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
-- The output from your entity
output: OUT STD_LOGIC
);
END example;
ARCHITECTURE behavior OF example IS
-- Define some constnts to help woth addressing when the design gets bigger
CONSTANT INPUT_1_ADDR : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000";
CONSTANT INPUT_2_ADDR : STD_LOGIC_VECTOR(2 DOWNTO 0) := "001";
-- I also find this constant helpful
CONSTANT ZEROS : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
-- Some registers to hold internal values
SIGNAL Input1 : STD_LOGIC;
SIGNAL Input2 : STD_LOGIC;
BEGIN
PROCESS(clk,nreset)
BEGIN
IF (nreset = '0') THEN
Input1 <= '0';
Input2 <= '0';
ELSIF (rising_edge(clk)) THEN
IF (Nios_Cs = '1' AND Nios_Wr = '1') THEN
CASE Nios_Addr IS
WHEN "000" =>
Input1 <= Nios_Din(0);
Input2 <= Input2;
WHEN "001" =>
Input1 <= Input1;
Input2 <= Nios_Din(1);
WHEN OTHERS =>
Input1 <= Input1;
Input2 <= Input2;
END CASE;
ELSE
Input1 <= Input1;
Input2 <= Input2;
END IF;
END IF;
END PROCESS;
Nios_Dout <= ZEROS(31 DOWNTO 1) & Input1 WHEN Nios_Cs = '1' AND Nios_Rd = '1' AND Nios_Addr = INPUT_1_ADDR ELSE
ZEROS(31 DOWNTO 1) & Input2 WHEN Nios_Cs = '1' AND Nios_Rd = '1' AND Nios_Addr = INPUT_2_ADDR ELSE
(OTHERS => '0');
output <= Input1 AND Input2
END behavior; This code generates a peripheral with two registers. You need to add it to your SOPC builder system and assign it with an address. You'll be able to access it from sw the same way you access any other address (with IOWR and IORD commands). Hope this helps. Nir