How to transfer data from FPGA to HPS and vice-versa in Cyclone V

This targets Arria 10 SoC but from an interface perspective is similar to Cyclone V SoC: https://www.altera.com/support/support-resources/design-examples/soc/fpga-to-hps-bridges-design-example.html

You are probably better off putting a DMA engine in the FPGA side of the design and have it push/pull data between the FPGA and HPS. If you want the FPGA to have a cacheable view of the data then have the logic access the F2H bridge and make sure the mastering logic performs cacheable accesses to the ACP mapper memory range at 0x8000_0000-0xBFFF_FFFF which you can remap to any 1GB window inside the MPU view of the memory (design above does this slightly differently in A10 SoC).

If you don't need cacheable data then your highest speed path will be the FPGA-to-SDRAM interface. In Cyclone V SoC you can have up to 4 64-bit AXI ports or gang them together into dual 128-bit or a single 256-bit interface. If you use Avalon-MM then you can have read-only or write-only ports as well, just remember each port consumes a command port (there are 6) and for reads and writes they consume a data port each (there are 4 for writes and 4 for reads).