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ETS is a neat concept but it is used for signal frequencies in the MHz. If your sinewave is 50Hz, then you have no reason to be using ETS.
1) What is the FPGA's sample frequency. If your base clock is 50MHz, then even by sampling with NIOS you should get at least 10kHz (just approximating) of ADC sampling rate. Use a timer to trigger ADC reads (in the timer ISR)
2) Buffer the samples in a FIFO, on chip ram, or sdram
3) Transmit data from FIFO to PC using USB (what is your baud rate - 9600, 115200 ??).
4) Reconstruct in Matlab - you know the sampling rate of your data (see 1), you can reconstruct your signal - there will be a delay but that shouldn't be a problem, unless you want exactly real time....
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Hi Krasner, sorry for poor understanding, I just read carefully about ETS and you are absolutely right about ETS being not a good option here... So, I wanted to go for the buffering approach you are stating here, I found a few references, I checked at the Qsys, there are a few built-in fifo
1.Can we combine both uart ip core with fifo core, or do you mean they are to be done separately?
2. I am confused whether I should use an avalon fifoed uart or any fifo will do? I know there is on-chip fifo memory in Qsys, i am using SDRAM in my system
3. May I know why do I need on-chip fifo memory core? Can we just buffer the data in SDRAM?
4. do you mind to send me link about design examples that use fifo?
Appreciate your time, thank you very much.
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