How to read output port?

there are two cases for ports:

1. port signals are connected to real in/outputs of fpga

( i think it's ok to use tristate signals to read back the setting of

the outputs)

2. port signals are used internal in fpga

(tristate does not make sense, I don't know if quartus syntesizes

tristate registers away ?)

because I had some signals with case 2 and also wanted to read back

the settings of the outputs, i made ports with input and output

(no tristate) and connected in/outputs of these ports together

in the top schematic.

perhaps someone from altera can explain what will happen if i use tristate for

internal port signals ?