How to read a 24-bit signed signal from VHDL block fed in Nios II system - always +ve

Yes that was a typo and yours is the correct version.

Is the qsys generated hdl file your top level or do you instantiate it in another source file. If you instantiate it in another file you can use the idea from TCWORLD to sign extend the reading in the hardware automatically. Then your reads of the 24 bit signal will always be extended to 32 bits.

If the qsys output is named MyNios then a top level file would work like this

constant cA2dDataBusMSB :natural := 23;

constant cNiosBusMSB : natural := 31;

sAdcData(cA2dDataBusMSB : 0 <= adc_pins(cA2dDataBusMSB downto 0);

-- Bridge the difference between the NIOS bus width and the ADC bus width.

BridgeBus:

for busbit in 1 to (cNiosBusMSB-cA2dDataBusMSB ) generate -- Generate 8 bits

sAdcData(busbit+cA2dDataBusMSB ) <= not adc_pins(cA2dDataBusMSB); -- replicate bit 23 onto bits 24 through 31.

end generate;

Hope this helps