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DO NOT TOUCH CONTENTS OF THAT FILE. Usually, it is already read-only.
You have to generate 125MHz Yourself and supply that clock to the mii/gmii mux core. It's simple to read comments and undestand how it work. Do that instead of asking in forum. Ask here things that You can't get running, but not things, that You don't understand.
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In Ethernet RX PLL, the inclk--enet_rx_clk is 125MHz, the outclk--c2(enet_tx_clk_phy) is also 125MHz. And enet_tx_clk_phy is the outclock of ddr_o phy_ckgen .As follows:
***************************************
ddr_o phy_ckgen
(
.datain_h(1'b1),
.datain_l(1'b0),
.outclock(enet_tx_clk_phy),
.dataout(enet_gtx_clk)
);
// Ethernet RX PLL
enet_rx_clk_pll enet_rx_clk_pll
(
.inclk0(enet_rx_clk),
.c0(enet_rx_clk_270deg),
.c1(enet_tx_clk_mac),
.c2(enet_tx_clk_phy)
);
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I was really confused why 1000Mbps isn't work.
Honored Contributor
