How to manage multiple clocks in the same bank that each require their own PLL?

I'm working on a Cyclone V GX9 device and I have two input clocks in the same bank. One of these clocks is used by the Nios and a PLL is required for SDRAM clocking. The other clock is referenced to serial data and requires it own, separate PLL.

By default, the fitter maps FRACTIONALPLL_X121_Y1_N0 to the SDRAM PLL, this leaves the other clock generating the following error.

Error (177020): The PLL reference clock was not placed in a dedicated input pin that can reach the fractional PLL

I have tried forcing the clocks to other PLLs with the SET_LOCATION command. Unsurprisingly, I get the same error.

Unfortunately, I'm not in a position where I can change the pin locations of the clocks. Any advice on how to successfully get this signals out to another PLL?