How to make sure nios send a single cycle control signal to peripheral?

I notice that read/write operation does not use a single clk cycle from the output and ive also read it in avalon bus specification. but im still quite confuse how with a IOWR operation i can make sure that only a single pulse of CNT_UP signal will be catch by my customHW(counter). should i like check an edge of the signal from avalon bus inside my avalon_counter interface?

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Second, in some cases, when accessing a 8-bit bus, the NIOS CPU performs 4 accesses to get a 32-bit value. I don't remember in which cases it does it, but now I don't bother anymore and always use 32-bit data busses even if I just have 8-bit values to exchange.

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but isnt IORD_8DIRECT macro specificly means we accessing 8bit. or it still access 32 bit but masked the 8bit LSB?