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I can do any 8/16/32bit accesses to any byte, or bytes, within the word all day long as long as the base address is 32bit aligned. If the address is 8/16 bit aligned, but not 32bit alligned, then I cannot do any accesses.
Is there a setting somewhere that forces that all address must be 32bit aligned?
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I did some experimenting and the problem is not with your software or component.
What I found was if you connect your component on a bus in parallel with wider components, it looks like the automatically generated Qsys adaptation modules are applying 32-bit alignment and your 8-bit writes to non-32-bit-aligned addresses are getting "lost" (specifically, altera_merlin_master_agent.sv). The issue might be straightforward like the address alignment depends on the bus width of the master (32-bit master -> 32-bit alignment, 64-bit master -> 64-bit alignment, ...).
The only arrangement that I found that would work is to insert a Clock Crossing bridge with 8-bit data bus width between the wider bus and the narrower 8-bit components.
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