How to implement very basic custom QSys component

I tried the following with the following success, or lack there of. (I changed the name just in case you see the difference)

alt_u8 *my_register = (unsigned char*)alt_remap_uncached((void*)DE0NANOLEDS_BASE,sizeof(alt_u8));

IOWR_ALTERA_AVALON_PIO_DATA(DE0NANOLEDS_BASE, (cnt) & 0xF);

IOWR_8DIRECT(DE0NANOLEDS_BASE, 0, (cnt) & 0xF);

*my_register = ((cnt) & 0xF);

With address on a 32bit boundary

IOWR_ALTERA_AVALON_PIO_DATA(DE0NANOLEDS_BASE, (cnt) & 0xF); <-- The write does not occur

IOWR_8DIRECT(DE0NANOLEDS_BASE, 0, (cnt) & 0xF); <-- The write does occur

*my_register = ((cnt) & 0xF); <-- The write does occur

With address on a 8bit boundary =># define DE0NANOLEDS_BASE 0x40018e9

None of the accesses generate a write.

I can do any 8/16/32bit accesses to any byte, or bytes, within the word all day long as long as the base address is 32bit aligned. If the address is 8/16 bit aligned, but not 32bit alligned, then I cannot do any accesses.

Is there a setting somewhere that forces that all address must be 32bit aligned?