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Try declaring my_register as a alt_u32.
Your custom component doesn't care of addr nor byte enable signals. Since Avalon is a 32bit bus, I guess the 8bit access could possibly write inconsistent data because Nios actually generates 4 8bit writes to complete the 32bit word.
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Ok...I tried the alt_u32 as follows:
alt_u32 *my_register = (unsigned char*)alt_remap_uncached((void*)LGLED_BASE,sizeof(alt_8));
and as
alt_u32 *my_register = (unsigned char*)alt_remap_uncached((void*)LGLED_BASE,sizeof(alt_u32));
Neither made a difference.
Why would the 8bit access possibly write inconsistent data. Even (in most cases I've seen) when a 32bit bus does 4 writes for a byte, typically the whole byte is applied across the entire bus thus writing the same byte value from each lane 4 times (maybe not the same for avalon\nios). Additionally, doesn't the avalon support 8bit access even on a 32bit bus? I thought the docs say it does and it support automatic bus sizing.
Just for clarity.
I did try (just to make sure my vhld was compiled in) tying two of the LEDs to the reset and the write. The reset shows inactive as I would expect and the write I'm sure I can't see because of the speed.
In any case, the suggested solution made no changes. It appears like the write never occurs. To test this, I implemented a latch on the write and routed it to one of the Leds. It doesn't occur. The Vhdl code never sees the write signal. Because of this, I dropped in a counter and check that the clock was there, and it is. So it just the write that is not happening as I would expect.
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