how to embeded the Nios software into FPGA sof file?

hi, Stewart, thanks! Now I solved the first problem, just re-build the whole Nios project, still select the on-chip RAM, it can work, I don't know why.

For the second problem, I'm doing another test, I tried to create a jic file in which two sof files are invloved, with either one of the sof files FPGA can works and can boot from EPCS, but FPGA cannot boot from EPCS with the new jic file, I just followed the guidance found in Altera Wiki, it cannot work.