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rshal2's avatar
rshal2
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

How to disable MAC-PHY communication ?

Hello, I am not sure why do we get "TSEMAC SW reset bit never cleared!" : We are connecting the FPGA to network switch, (unmanaged switch), so we removed all communication with phy , by disabling M...
FawazJ_Altera's avatar
FawazJ_Altera
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Hello,

I will investigate more about your problem. In the mean time, would you please confirm the clock connections that are going to TSE, including the ones that are coming from the PHY?

thank you

rshal2's avatar
rshal2
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Thank you very much, It's very much appreciated.

As to the clocks, the FPGA internal clocks seems to be OK.

Is there a specific clock that we should check ?

nios_eth_tse_pcs_mac_tx_clock_clk => emac_tx_clk,
   nios_eth_tse_pcs_mac_rx_clock_clk => rgmii_rx_clk,

I've validated with signal tap that emac_tx_clk is correct (25M clock for 100M ethernet)

as to rgmii_rx_clk, I see no clock, does it explain the mac reset issue ? not sure

Thank you