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Honored Contributor
Honored ContributorHow to design with one fixed wait state
I design the Avalon bus wrapper with fundamental slave read transfers.
How do I design this wrapper with one fixed wait state?In the Avalon Bus Specification,it's time reference description after the readn wait two clock, and read data.How can i let readn become two clock?Am I revise the PTF file?1 Reply
Altera_ForumHi genchen,
in the component editor->interfaces u can specify read wait in clock cycles.
