Altera_ForumHonored Contributor20 years agoHow to design with one fixed wait state I design the Avalon bus wrapper with fundamental slave read transfers. How do I design this wrapper with one fixed wait state?In the Avalon Bus Specification,it's time reference description...Show More
Altera_ForumHonored Contributor20 years agoHi genchen, in the component editor->interfaces u can specify read wait in clock cycles.
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